Gregory explains the principles of clock recovery and clock synchronization. A digital PLL is designed as a full clock recovery system that is demonstrated on the bench. In digital communication, where data messages are transmitted encoded in bitstreams, the receiver end is always presented with the challenge of clock recovery. Clock recovery is the art of reestablishing the time slices of the encoded bits, that were generated in the transmitter side. This timing information, for NRZ signals, is not transmitted, because it would occupy bandwidth without payload information. Read the full article here: https://gusbertianalog.com/clock-recovery-with-digital-pll/ 00:24 - Introduction 01:18 - NRZ bitstream signal 02:25 - Why Clock Recovery and Synchronization 05:40 - Edge detection on the data bitstream 08:12 - Digital PLL 13:35 - Designed system 15:30 - Data frame sync Support the channel being a Patron! https://patreon.com/allelectronics Follow All Electronics on Instagram: https://instagram.com/allelectronicsgr References: http://s53mv.s56g.net/dmostovi.pdf https://en.wikipedia.org/wiki/Clock_recovery https://download.tek.com/document/65W_26023_0_Letter.pdf https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/Old/Older/lect_17_CDR_2up.pdf https://www.skylaneoptics.com/en/articles/clock-data-recovery-cdr/