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Techno Tutorials ( e-Learning)

Digital Electronics BEU

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Last updated on Mar 4, 2024
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Fundamental of electronics engineering  one Shot Video | Unit 4: Digital Electronics| Part 1
1:09:25
Unit 1 L6.1 | Logic Gates | NOT, OR, AND, NAND,NOR, XOR, XNOR | Universal Gates | DSD
25:36
Unit 1 L 7.1 | Boolean Algebra | Properties of Boolean Algebra | Demorgan's theorem
17:44
Unit 1 L8 | DeMorgan's Theorem | DeMorgan's Law | Application of DeMorgan's Theorem
8:53
unit 1 L1.1 | Decimal to Binary Conversion | Binary to Decimal Conversion | KEC201T | KEC 302
7:46
U1 L1.2 |  Decimal To Octal | Decimal to Hexadecimal | decimal to different base conversion
11:31
U1 L1.3 | Decimal to Hexadecimal code conversion | Hexadecimal to Decimal Code Conversion
7:56
U1L1.4 | Find base of number system if solution to the Quadratic Equation x²+11x+22=0 are x=3 & x=6
3:27
Unit 1 L2 | Weighted Code | Non- weighted Codes | Excess 3 Code | BCD Code| DSD KEC 302
10:58
Unit 1 L3 | r' and (r-1)'s Complement | 1's & 2's complement | 9's & 10's complement | 7's & 8's
10:45
Unit 1 L4 | Subtraction using 1's Complement | 2's and 1's  Complement Subtraction | KEC 302
10:37
Parity bit | error detection and correction |Even parity | Odd parity
4:09
Even Parity Generator | 3 Bit Even Parity generator
5:56
Even parity Checker | Design a even Parity Checker | 4 Bit even parity checker
9:59
Parity Generator | 3 Bit Odd Parity Generator | Odd Parity Generator | Design odd Parity Generator
5:50
U1L8 | Hamming codeword Generation | Hamming Code | Error Control Coding
13:13
unit 1 L9 | Error detection and correction in hamming code words | Hamming code
8:49
U4L2 | Characteristic of Logic families I Noise margin | Propagation Delay| Noise Immunity | FAN OUT
12:34
U4 L3 | BJT as inverter | working of BJT as inverter | How BJT can be used as inverter
9:39
U5L5 | TTL With open collector | Transistor Transistor Logic open collector | 2 input TTL NAND Gate
14:14
U4 L4 | TTL NAND Gate with Totem Pole Output | TTL totem pole explanation  | 2 input TTL NAND Gate
15:45
U4 L5 | Tri State TTL | TTL Tri- state inverter | Logic family | Transistor Transistor logic |TTL
14:32
K-map minterms | important  for k-map | k-map
1:00
K-map | Karnaugh Map | 3 Variable K-map | 4 Variable K-map | 5 Variable K-map | 6 Variable K-map
22:25
unit 1 L12.3 | How to solve boolean expression using K-Map | simplify boolean expression using K-Map
8:12
U2L4.1 | Multiplexers | 2:1 Multiplexer | 4:1 Multiplexer | logic diagram of 2 x 1 Multiplexer
11:41
U2L4.2 | Implement Boolean function using Multiplexer | 3 variable function  using 8:1& 4:1 MUX
8:13
4 : 1 multiplexer using 2 : 1 multiplexer | 4 X1 using 2X1 multiplexer | 4 :1 using 2 :1 MUX
5:57
Boolean function implementation using Multiplexer | Using 8X1Mux | using 4X1 | AKTU DSD
15:57
U2 L3.2| 4:1 multiplexer using Gates | 4:1 multiplexer using nand | 4 X 1 Multiplexer using Gates
6:39
U2L5.1 | Demultiplexer | 1:4 Demultiplexer | logic diagram of 1:4 DEMUX | Demultiplexer using GATES
6:52
U2L5.2 |1:4 Demultiplexer using 1:2 Demultiplexer | Demultiplexer tree | 1 X 4 Demux using 1X2 Demux
7:00
U2L4.3 | 1:16 Demultiplexer using 1:4 Demux | 1 X16 Demux Using 1 X 4 Demux |1:4 Demux to 1:16 Demux
9:25
U2L7.1| 3 to 8 Decoder Using Gates | Design of 3 X 8 Decoder | Binary to Octal Decoder | 3:8 Decoder
10:09
U2L5.4 | BCD to Seven Segment Decoder| BCD to Seven Segment Display| BCD TO 7 Segment common cathode
22:39
Unit 2 | DSD & DE one shot part 1 | Adders in one shot | BCD adder | parallel adder | serial adder
41:52
Half subtractor using NAND Gates | Half subtractor using NOR gates only | AKTU 2021-22 | question1.d
10:08
U2L8.3 | Half subtractor | 2 Bit Binary Subtractor | Half subtractor using Logic Gates
6:05
Full Subtractor  | using half subtractor | Implementation  Full Subtractor Using Half Subtractor
6:36
U2 L8.4 | Full subtractor circuit | Full subtractor using Gates | FULL SUBTRACTOR
12:57
U2 L9.2 | 4 Bit Parallel Subtractor | 4 Bit Parallel subtractor using Full Adder
12:03
U2 L10 | BCD ADDER | Decimal adder | BCD ADDITION | Binary Adder
17:01
Unit 1 L5.1 | BCD Addition | How to perform BCD addition | Example of Binary Coded Decimal Addition
7:19
U2 L9.4 |  Carry look ahead adder | Carry Look Ahead Adder | Carry Look Ahead Generator
17:30
U2 L8.5 | Serial Adder | DSD | Digital electronics | Serial Adder with accumulator
8:13
U2 L12 | ALU | Arithmetic logic Unit | DSD | UNIT 2 | combinational circuit
9:25
U2L2.2 | 3 Bit Gray to Binary Code Converter | Gray to Binary Code Converter | Code converter
11:01
U2L2.3 | 4 bit Binary to Gray Code Converter | Binary to Gray code Converter | Digital system
10:14
U2 L2.5 | BCD to Gray Code Converter | Design a BCD to Gray | DLD Code Converter
9:35
U2 L6.2 | | Priority Encoder | 4 to 2  Priority Encoder | Priority Encoder: Truth Table, K-Map
7:13
Two Bit magnitude Comparator using Decoder | Magnitude Comparator
8:10
U2L3.3 | 3 Bit Magnitude Comparator | 3-Bit comparator | Design 3-Bit magnitude comparator
40:45
U2L3.4 | 4 Bit Magnitude Comparator | Magnitude Comparator | Design a 4-Bit Magnitude Comparator
18:01
U3L1.1 | Differance between combinational and sequential circuit| Combinational & sequential circuit
7:34
U3L1.2 | Latch & Flip Flop | Difference  between Latch and Flip Flop | distinguish latch & flip flop
5:42
U3 L2.1 I SR LATCH using NOR gate(Part 1) | SR LATCH | Basic of Flip flop | SR Flip flop
12:38
U3L2.2 | S-R FLIP FLOP in hindi | SR latch with control input | Set Reset latch |Set Reset FLIP FLOP
22:07
U3L2.3 | D Flip Flop | delay flip flop | Transparent Flip Flop | WORKING OF D FLIP FLOP
11:44
U3L2.4 | T flip flop | timing diagram  | State table| Excitation table |characteristic equation
9:09
U3L2.5 | JK FLIP FLOP | working of JK flip flop | JK Flip Flop Using NAND gate
13:11
U3L2.6 | Race around condition in JK FLIP FLOP | WHAT IS RACE AROUND CONDITION
8:20
Unit 3 L2.7 | Master Slave JK flip flop | Master slave Waveform  | Master slave using JK flip flop
8:48
U3 L7.1 | Introduction of shift register | SHIFT REGISTER
8:30
U3L7.2 | SISO | Serial In serial Out shift Register | RIGHT SHIFT
15:06
U3 L7.4  | PISO | Parallel In Serial Out Shift Register | Shift register
11:11
U3 L7.5 | Parallel in Parallel Out Shift Registers | PIPO
6:11
U3 L8 | Bidirectional shift register | 4-Bit Bidirectional Shift Register with Parallel Load
13:32
U3L9 | Universal Shift Register | Universal Shift register  | universal shift register using D FF
15:55
U3 L4.1 | Define Counter | Introduction to counter | WHAT IS COUNTER
4:58
U3 L5 | Ring counter | 4 Bit Ring Counter | Shift Register Counter | MOD 4 Ring Counter
13:08
U3L4.6 | MOD 8 Synchronous Counter Using JK Flip Flop  | MOD 8 Counter | 3 Bit Synchronous counter
12:32
U3L4.4 | MOD-5 Asynchronous Counter | Mod 5 Ripple counter using JK Flip flop | MODulo-5 counter
10:02
3 bit Up/Down Ripple Counter | 3 Bit Asynchronous Up/Down Counter | Mod 8 Ripple Up/Down Counter
7:14
MOD-8 Synchronous Down counter Using D flip flop | 3-Bit Synchronous Down counter
9:24
U5 L1 | introduction of Digital to Analog converter | Example of DAC
8:29
U5 L3 | Binary Weighted Resistor DAC
13:23
U5 L4 | R-2R ladder DAC | Working of R-2R Ladder DAC | Digital to analog Converter
18:37
U5 L2 | Specifications of D/A converter | Resolution, Accuracy, linearity , temperature sensitivity
12:52
U5 L6 | Successive Approximation ADC | SAR ADC | DSD UNIT 5 | Analog to Digital Coverter
12:02
U5 L5 | Dual Slope  Analog to Digital Converter | Integrator Type ADC | Dual slope ADC in hindi
23:24
U5 L7 | Flash Type ADC  | Parallel ADC | Analog to Digital Converter | Digital Electronics
13:35
U4 L11.1 | Programmable Logic Devices ( Introduction) | PLD | CAO KEC051 | DSD KEC302
6:36
U4 L11.2 | PLA (Programmable logic array) | PAL (Programmable array logic) | PROM Example |  PLD
10:28
Signed number representation | Representation of signed numbers| Signed Magnitude | DE | DSD | CAO
11:08
Boolean function Implementation using Multiplexer | POS (product of Sum ) function implementation
4:16